1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device including a semiconductor element having an insulated gate field effect portion.
2. Description of the Background Art
A power semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a diode is used as a semiconductor device for electric power applications. In order to reduce loss at the time of application of power, lower resistance and operation at higher speed are required in the power semiconductor element. In general, lower resistance and operation at higher speed are mutually contradictory in the power semiconductor element, and it has been difficult to manufacture a power semiconductor element having characteristics excellent in both of lower resistance and operation at higher speed.
For example, Japanese Patent Laying-Open No. 08-288303 (Patent Document 1) discloses a technique aiming to simultaneously achieve operation at higher speed and lower ON resistance. Patent Document 1 discloses a vertical field effect transistor including a high-concentration impurity region of a conductivity type opposite to a base region (third impurity diffusion region) at a side portion of the base region (second impurity diffusion region).
In addition, for example, Japanese Patent Laying-Open No. 10-242458 (Patent Document 2), Japanese Patent Laying-Open No. 08-125172 (Patent Document 3), and the like also disclose a structure where a high-concentration impurity region is formed at the side portion of the base region as described above.
Meanwhile, Japanese Patent Laying-Open No. 03-029328 (Patent Document 4) discloses, as a technique to lower a feedback capacitance, a Schottky-junction field effect transistor that has a protection film of a thickness smaller in an active region than in an inactive region.
According to Patent Documents 1 to 3 above, though an ON voltage is lowered by the high-concentration impurity region formed at the side portion of the base region, it is difficult to achieve operation at higher speed, as will be described below.
In order to achieve operation at higher speed, it is necessary to lower a feedback capacitance. Here, the feedback capacitance refers to the sum of an insulating film capacitance produced between a gate electrode and a base region with an insulating film being interposed and a depletion capacitance produced in a region where a depletion layer extends at a pn junction between the base region and a region at the side portion thereof. In Patent Documents 1 to 3 above, as the high-concentration region provided at the side portion of the base region contains a large amount of carrier, extension of the depletion layer from the pn junction between the base region and the high-concentration region to the high-concentration region is restricted. Accordingly, if the high-concentration region extends over the entire side portion of the base region in Patent Documents 1 to 3, extension of the depletion layer is restricted along the entire side portion of the base region, and consequently the depletion capacitance increases in the high-concentration region and hence the feedback capacitance increases. Therefore, operation at higher speed cannot be achieved due to the increase in the feedback capacitance.
According to Patent Document 4 above, the feedback capacitance can be lowered by lowering the insulating film capacitance. A technique to lower an ON voltage in a region where a channel is formed, however, is not disclosed, and the ON voltage is disadvantageously high.